Reconfigurable DC-DC Converter with Fault-Tolerant Capability


Research Fellow: John Long Soon | Advisor: Jimmy. C. -H. Peng | Collaborators: Dylan D. -C. Lu, University of Sydney Technology, Australia, and Weidong Xiao, University of Sydney, Australia | Project Duration: 2019-2020 

Reliability of power electronic converters system (PECS) is one of the highest importance in mission-critical applications such as aerospace devices, medical equipment, electric vehicles, and distributed generation units. Therefore, it becomes essential to incorporate fault-tolerant (FT) techniques in the design stage and eventually improve system resilience against unpredictable failures. The demand for dc-dc conversion–both step-up and step-down–has been increasing in the recent past due to its use in photo-voltaic generation, battery systems, and dc-based loads for instance. In this research study, we focus on increasing the operational reliability of dc-dc converters using a FT design.

Figure 1. Overview of the Proposed FT design (a) The conventional buck converter. (b) The proposed FT converter with 1-level redundancy (c) Step-down operation of the FT converter. (d) Step-up operation of the FT converter.

Malfunction of power semiconductor switches is the dominant cause of failure in power electronic converters. This research proposes a novel dual switch dc-dc topology for high reliability applications. The proposed converter is fault-tolerant and supports operation under both step-down and step-up modes as shown in Figure 1. The proposed topology can be reconfigured automatically under various switch-fault conditions in order to maintain normal operation.

An FT scheme generally entails the two stages–fault detection, and remedial action. The former identifies and isolates the existence of a fault, while the latter reconfigures the converter to ensure service continuity. The ideal FT solution should be cost-effective and minimal additional power losses. Studies in the past have shown that the malfunction of power semiconductors is the main cause of converter faults.

This is achieved through modification of the buck topology, shown Figure 1(a), by utilizing a single redundant switch, illustrated in Figure 1(b), which is both cost-effective and achieves high reliability. Hardware redundancy is an effective way to improve the reliability of converters by avoiding disruptions arising from a single-point failure for the instance of a switch fault. 

Reliability Evaluation

Reliability assessment of the proposed converter is evaluated theoretically using a Markov model, demonstrating its superiority over conventional topologies. A Markov chain uses directed graphs to visualize the probability of transitioning from one state to another within a finite number of possible states. In the literature, various FT converter topologies have been extensively studied using Markov models to evaluate the operational lifetime vs. system reliability based on the mean-time-to-failure (MTTF) profile.

Figure 2. Reliability model of power converters based on a Markov chain. (a) The conventional buck converter consisting of three possible states and three transition paths. (b) The proposed FT converter with 1-level redundancy, consisting of five possible states and eight transition paths.

a. Conventional DC-DC Converter

The states and their transition paths for a single-switch conventional buck converter are shown in Figure 2(a). The states considered here are defined as follows. State 1 refers to the condition when the converter is ‘Healthy’, State 2 refers to the presence of a ‘Partial fault’ in the converter, while State 3 refers to a ‘Complete Fault’ in the converter.

A transition matrix defines the probability of a state transition from one state to another, for all possible combinations of starting and ending states. The dimensions of the transition matrix correspond to the number of possible states, which is 3 in this case. The transition matrix of the conventional converter can be modeled as:




b. Proposed FT Converter with 1-level redundant switch


Figure 2(b) shows the Markov chain of the proposed FT can be expanded into five possible states and eight transition paths. The transition path λ13 represents the scenario when the proposed FT converter reconfigures from buck to buck-boost operation when S1 fails to operate and F1 blows. Note that this particular switch failure will not force the converter to the absorption state 5 due to the presence of the redundant switch S2. Next, the transition paths with λ12 and λ34 indicate the transition of the converter under buck and buck-boost modes from a healthy to a degradation state, respectively. Furthermore, λ24 is when the converter reconfigures from S1 (buck) to S2 (buck-boost), while the converter still suffers from a partial fault. The absorption state can happen through the following four transition paths; λ15, λ25, λ35, and λ45. In this case, λ35 and λ45 refer to the failure of the last redundant switch S2 from healthy and degradation conditions, respectively. The transition matrix of the proposed FT converter with 1-level redundancy can be modeled as:



The converter is initially assumed to be healthy, and the probability P1(0) is assigned as '1'. The initial probability vector of all n states can be formulated as:


The reliability function and MTTF profile of the proposed FT converter with 1-level redundancy can be derived as:



Numerical Reliability Assessment

This section presents a numerical reliability assessment of the proposed FT converter and the conventional converter based on the typical failure rates observed for the various components. Table I lists the numerical values regarding the converter reliability profile. These probabilities data is computed based on each of the transition paths of the Markov chain model, and referring to the experimental conditions.

Table I. Reliability profile between conventional and proposed FT converters.

Figure 3 illustrates the reliability comparison between a conventional buck converter and the proposed FT converter under different redundancy levels. The exponential distribution curve shown in below, which demonstrates that the proposed FT converter has a longer lifetime than the conventional converter. Furthermore, increasing the level of redundancy will guarantee higher reliability, which may be suitable for critical industrial applications.

Figure 3. Reliability comparison between the conventional and the proposed FT converters

Figure 4 presents the proposed digital control scheme including the functions of fault-detection, and voltage regulation. The FT control structure is coordinated by the micro-controller for re-configuring the redundant switch when an S1 fault occurs. A feedback controller of the proposed converter (with one-level redundancy) is designed for the buck-boost mode in this case study. The affine parameterization can now be utilized to synthesize the PID controller. The controller, Cpid(s), is represented as follows:

Figure 4. Simplified FT control diagram showing the proposed (a) fault-detection (FD) scheme, and (b) reconfiguration of the feedback controller.

Table II. Parameter of the PID controller for the reconfigurable FT converter.

Here, ζCL is the damping ratio closely related to the overshoot performance, It can usually be assigned a value from 0.7 to 1 for obtaining the desired closed-loop performance. KG is the scaling factor to adjust the gain of ζCL, which impacts the response speed of the closed-loop system. Table II shows that the parameters of the PID controller are varied by the two variables ζCL and ωCL. With this design, the performance of the controller is practically tested for illustrating the effectiveness of the control tuning approach.

Experimental Verification

The performance of the proposed FT converter, transitioning from a healthy state to various faulty conditions, was evaluated using the prototype fault-detection and converter circuit shown in Figure 5. The fault detection circuit shown in Figure 4(a) measures the drain-source voltage Vds of the switch S1 to detect a fault. The simplified feedback control structure for FT reconfiguration illustrated in Figure 4(b) was implemented in the DSP controller TMS320F28335.

Figure 5. Experimental setup of the proposed FT converter. (Left) - Laboratory equipment to measure the (Output voltage, Inductor current and Fault detection signal) and (Right) - PCB prototype of the FT DC-DC converter.

Initially, a short-circuit fault (SCF) between the drain-source (Vds) terminals of S1 was triggered at 500 ms as shown in Figure 6. Consequently, the F1 fuse blew, and the S1 fault was detected by comparing the PWM signal of the gate driver Vgs with Vds. The propagation delay of the gate driver and inverter gate caused a mismatch Vds_nand signal. In this case, the Vds_dflip is compensated through the D-flip flop, shown in Figure 4(a), by injecting the input clock signal to fill the mismatching signal gap. This ensures that the S-R latch could properly activate the FT reconfiguration when S1 failed. Subsequently, the signal Q became 1 and triggered the buck-boost mode, i.e., the SCF was detected. Note that the FD time was around 2.5 μs, which was less than the switching period.

Figure 6. A short-circuit fault is triggered at 500 ms, and the fault detection time is around 2.5 us.

Figure 7. Waveforms of the proposed FT converter when transitioning from the buck mode to the buck-boost mode after an SCF at 500ms.

The output performance of the step-down mode of the reconfigured FT converter is illustrated in Figure 7. The large overshoots observed in Vo and iL during the transition period were the outcome of using the overshoot parameters listed in Table II. In addition, the zoomed-in waveforms of the S2-PWM signal and iL exhibited time-varying duty cycles and fluctuating currents, respectively. These fluctuating dynamics led to additional power losses induced by the switching noise. Furthermore, overshoots (voltage and current spikes) could cause physical damages to other electronic components, and consequently reduce the overall lifespan of the converter. In contrast, for the undershoot control parameters, the smoother iL and Vo waveforms after the reconfiguration reduced the component stress. However, the reconfiguration speed was slower than the overshoot counterpart. The larger corresponding voltage dip of Vo may also cause a downtime to the connected load. This demonstrates the need for affine parameterization to achieve the desired transition dynamics.

Figuew 8. Waveforms of the proposed FT converter transitioning from the buck mode to the buck-boost mode after an SCF at 500ms using affine parameters.

Figure 9. Waveforms of the proposed FT converter transitioning from the boost mode to the buck-boost mode after an SCF at 1.3s. The converter experienced multiple input step changes.

The corresponding scopes of the affine controller are shown in Figure 8. This controller was able to achieve a more seamless and smoother reconfiguration. Specifically, the transitioning time was around 10ms compared to the overshoot and undershoot controllers of 50 ms and 100 ms, respectively. As a result, the lifetime reliability of the power converter is enhanced. The proposed converter was further demonstrated for a transition from the synchronous boost mode to the buck-boost mode in step-up FT operation. In this case, an SCF was triggered after 1.3 s, and the corresponding reconfiguration time was around 12 ms as shown in Figure 9. In this scenario, the affine controller also maintained Vo at 12V when the input voltage was varied between 9V to 6V , and iL was ramped up at different time intervals.

In summary, this research presented a new dc/dc topology to achieve not only the function of fault tolerance (FT), but also flexible voltage conversion for either step-down or step-up operation after a switch fault. Both objectives were achieved by simply adding one additional switch to the conventional buck converter. Thus, the overall component count is low in the proposed design in comparison with other FT approaches. Reliability assessment was performed using Markov chains, which indicated an improved reliability index and fault tolerant capability for the proposed design in response to switch failures. Further, to enhance the performance during steady state and while transitioning between healthy and reconfigured states (after a fault), affine parameterization was adopted. An experimental study was performed to illustrate the effectiveness of the proposed FT converter topology and control design.

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